In a digital communication apparatus, having a rack structure, such as a wireless base station apparatus or an exchanger, a status monitor unit is provided to each package, and an upper order status monitor unit monitors the package states at all times through this status monitor unit. For example, in the digital communication apparatus, shown in FIG. 5, there are provided a plurality of packages 128 and an upper order monitor unit 27, which upper order monitor unit monitors the status of the packages 128. Each of the packages 128 includes a status monitor unit 20, a power supply monitor circuit 21, a processor 22, a power-on reset circuit 23, a clock monitor circuit 24, a reset circuit 101, an AND gate circuit 26, other devices 25 and an external pull-up resistor 29.
The status monitor unit 20 reports the state of the package 128 to the upper order monitor unit 27. The power supply monitor circuit 21 monitors the power supply voltage of the package 128 and sets the external power-on reset signal PRSTB to a high level, abbreviated to ‘H’ hereinbelow, when the power supply voltage is not lower than a prescribed value, while setting the external power-on reset signal PRSTB to a low level, ‘abbreviated to ‘L’ hereinbelow, when the power supply voltage is lower than the prescribed value.
The processor 22 is such a device performing the processing in accordance with a pre-stored program, such as a CPU or a DSP (digital signal processor), and exercises control for various devices provided within the package 128. When the processor 22 has determined that the package 128 in its entirety needs to be reset (initialized), such as when the operation of the package 128 has become unstable such that re-setting (re-initializing) the package is necessary, the processor outputs a reset trigger signal CPURSTB from the PIO port to the reset circuit 101. In the explanation to follow, the reset trigger signal CPURSTB is an active low signal, so that, in resetting the package 128, the processor 22 performs the operation of setting the reset trigger signal CPURSTB, which is normally in a negated state indicating ‘H’ state, to an asserted state indicating ‘L’ state.
In general, when a signal line is in an effective or active state, such signal line is said to be asserted. When a signal line is in an ineffective or inactive state, such signal line is said to be negated. On the other hand, setting the signal line to the effective state or to the ineffective state is said to assert or negate the signal line, respectively.
The power-on reset circuit 23 generates an active low reset signal, based on the external power-on reset signal PRSTB from the power supply monitor circuit 21, to send the so generated signal to the AND gate circuit 26.
The clock monitor circuit 24 monitors clock signals, supplied to respective circuits in the package 128, and outputs, to the reset circuit 101, a clock stop detection signal CALMB, which is in the negated state indicating the ‘H’ state when the clock signals are operating normally, and which is in the asserted stat indicating the ‘L’ state when the clock signals are stopped.
The reset circuit 101 generates and outputs a reset output signal RSTB which takes on the level ‘L’ for a prescribed period when the reset trigger signal CPURSTB from the processor 22 takes on the level ‘L’.
The AND gate circuit 26 takes a logical product of the reset signal from the power-on reset circuit 23 and the reset output signal RSTB from the reset circuit 101 to send the results of the processing operation to the status monitor unit 20, the processor 22, and to the other devices 25. Since the reset signal from the power-on reset circuit 23 and the reset output signal RSTB from the reset circuit 101 are both active low signals, the output of the AND gate circuit 26 also transitions to ‘L’ indicative of an active state if any one of the signals is active.
In this digital communication system, the upper order state monitor unit 27 monitors the state of each package 128 through the status monitor unit 20 provided to each of the plural packages 128.
FIG. 6 shows the configuration of the reset circuit 101 shown in FIG. 5. Referring to FIG. 6, this conventional reset circuit 101 is made up by inverter circuits 7, 9, a reset extension circuit 3 and an AND gate circuit 10.
The inverter circuit 7 inverts the reset trigger signal CPURSTB from the processor 22 to output the resulting inverted signal to an input terminal IN of the reset extension circuit 3.
The reset extension circuit 3 detects a rise edge of an output of the inverter circuit 7 and generates a signal which remains ‘H’ for a predetermined time as from the rise edge to send out the so generated signal at its output terminal OUT. The reset extension circuit 3 is supplied with a clock stop detection signal CALMB, as an asynchronous clear signal C and, when the clock is in a stopped state and the clock stop detection signal CALMB transitions to ‘L’ indicating the asserted state, the reset extension circuit is initialized to set the output terminal OUT to ‘L’.
The inverter circuit 9 outputs to the AND gate circuit 10 a signal RSTB3 which is an inverted version of the output signal of the reset extension circuit 3.
The AND gate circuit 10 takes a logical product of the signal RSTB3 from the inverter circuit 9 and a signal RSTB4 of the same logic as the signal CPURSTB to send out the result of the operation as reset output signal RSTB.
FIG. 7 shows the configuration of the reset extension circuit 3 shown in FIG. 6. The reset extension circuit 3 is supplied with an input signal IN (active high signal), an external input clock CLK and an asynchronous clear signal C, as inputs, to output a reset extension signal OUT (active high signal). The asynchronous clear signal C is an active high signal for the reset extension circuit 3, such that, when the asynchronous clear signal C is H, the reset extension circuit performs the reset extending operation, whereas, when the asynchronous clear signal C is ‘L’, the reset extension circuit is initialized to set the output terminal OUT to ‘L’.
The reset extension circuit 3 is made up by a differentiating circuit 31, a counter circuit 32 and a JK flip-flop circuit 33.
The differentiating circuit 31 is supplied with the input signal IN, external input clock CLK and with the asynchronous clear signal C to detect the rise edge of the input signal IN to send out a pulse of one clock width, synchronized with the external input clock CLK, to the counter circuit 32 and to the JK flip-flop circuit 33.
The differentiating circuit 31 is made up by a D-flip-flop circuit 311, a D-flip-flop circuit 312, an inverter circuit 313 and an AND gate circuit 314.
The D-flip-flop circuit 311 is supplied with the input signal IN as a D input, with the external input clock CLK as input clock and with an asynchronous clear signal C as an asynchronous clear input (active high), to send out an output Q to the inverter circuit 313 and to the AND gate circuit 314. The inverter circuit 313 is supplied with the output of the D-flip-flop circuit 311 as an input and sends out its inverted version to the D-flip-flop circuit 312. This D-flip-flop circuit 312 is supplied with the output of the inverter circuit 313 at a D input, with the clock CLK as input clock and with the external input C as the asynchronous clear signal C (active high) to send out an output Q to the AND gate circuit 314. The AND gate circuit 314 is supplied with outputs of the D-flip-flop circuits 311, 312 as inputs to perform logical product processing thereon to send out the result of the operation as output of the differentiating circuit 31.
The counter circuit 32 is supplied with the output of the differentiating circuit 31 at an LD input, with the clock CLK as an external input clock and with an external input C as the asynchronous clear signal (active high signal), to send out an output OUT to the K input of the JK flip-flop circuit 33. When the asynchronous clear signal C is ‘H’, the counter circuit 32 initializes the counter function to output ‘L’ to the terminal OUT. When the asynchronous clear signal C is ‘L’, and the input at LD is ‘H’, an initial value is set in the counter with the rise of the external input clock CLK. When the LD input transitions to ‘L’, the counter counts up or down with each rise of the external input clock CLK. When the counter has reached a setting value, a signal ‘H’ is output with the rise of the clock CLK.
The JK flip-flop circuit 33 is supplied with an output of the differentiating circuit 31 at the J-input, with an output OUT of the counter circuit 32 at the K-input, with the clock CLK at an input clock terminal, and with an asynchronous clear signal C (active high signal) at an external clear input C, to send out a Q output at an output terminal OUT of the reset extension circuit 3.
The signal flow in the reset extension circuit 3 is such that transition from ‘L’ to ‘H’ of the external input IN is detected by the differentiating circuit 31 to output a pulse ‘H’, and the JK flip-flop circuit 33 outputs the output signal OUT in the ‘H’ state, based on the pulse ‘H’, at the same time as an initial value is set in the counter circuit 32. When the prescribed period of time as provided in the counter circuit 32 has elapsed, the counter circuit 32 outputs a signal ‘H’, as a result of which the output signal OUT of the JK flip-flop circuit 33 is set to ‘L’. Thus, the operation of the reset extension circuit 3 is such that ‘H’ is output as a signal OUT until a predetermined time has elapsed as from the rise edge of the input IN.
This operation of the reset extension circuit 3 will be explained by referring to the timing chart of FIG. 8.
When the reset trigger signal CPURSTB is asserted at timing of T0, the D-flip-flop circuit 311 of the differentiating circuit 31 outputs ‘H’ at FFOUT1 at a timing of T1 corresponding to the rise of the next clock. Since the output FFOUT2 of the D-flip-flop circuit 312 remains in the ‘H’ state at this time point, ‘H’ commences to be output in an output CIN of the differentiating circuit 31. At a timing of T2, FFOUT2 takes on the level ‘L’, so that CIN also transitions to ‘L’. Since the J-input of the JK flip-flop circuit 33 is ‘H’ at this timing of T2, the Q-output of the JK flip-flop circuit 33 takes on the level ‘H’, while RSTB1 and the reset output signal RSTB become ‘L’ as from timing of T2, thus asserting the reset output signal RSTB. With the reset output signal RSTB thus asserted, the PIO port output of the processor 22 is initialized as input port and hence undergoes transition gradually to ‘H’ by the external pull-up resistor 29.
The shaded parts of the reset trigger signal CPURSTB in FIG. 8 indicates that the time for transition to ‘H’ differs with the constants of the pull-up resistor 29 or with the values of device capacitances. Hence, FFOUT1 and FFOUT2 may take ‘H’ or ‘L’ during the time as indicated by shaded parts. However, this has nothing to do with the operation as the reset extension circuit 3, since the output CIN of the differentiating circuit 31 necessarily outputs ‘H’ only during the time as from timing of T1 until timing of T2.
Since CIN is ‘L’ at the timing of T3, the counter circuit 32 starts counting up or down. At timing of T4, the predetermined time Td as set by the counter circuit 32 as from the timing of T3 has elapsed. At this timing of T4, the counter circuit 32 provided in the reset extension circuit 3 has timed out to output ‘H’ at the output terminal OUT. Thus, at a timing of T5, the output Q of the JK flip-flop circuit 33, provided in the reset extension circuit 3, takes on the level ‘L’, while the reset output signal RSTB takes on the level ‘H’, thus stopping reset extension.
If the reset trigger signal CPURSTB from the processor 22 is entered to the above-described conventional reset circuit 101, the reset output signal RSTB, which is set to the asserted state (‘L’ state) only for a predetermined time by the reset extension circuit 3 provided in its inside, is generated and output. The reason is that, in order for e.g., the other devices 25 to perform the normal reset operations, there is provided a minimum prescribed time period in which the reset output signal RSTB is to remain in the ‘L’ state, and that, for assuring the normal reset operations, the reset output signal RSTB must be in the ‘L’ state for a time duration not shorter than this prescribed time period.
Since the status monitor unit 20 reports the status of the package 128 to the upper order state monitor unit 27, it is necessary for the status monitor unit to be in operation even when the package 128 is malfunctioning, in order to continue the monitoring of the status of the package 128. Such malfunctioning state includes states in which clocks have ceased to be supplied to the processor 22 or to the reset circuit 101. Thus, in case the clocks are stopped during the time the reset circuit 101 is performing the operation for reset extension, the clock stop detection signal CALMB takes on the level ‘L’ to initialize the reset extension circuit 3 to set the output terminal OUT to ‘L’ to stop the reset extension of the reset circuit 101.
However, if the reset extension circuit 3 is reset by the clock supply cessation, such that the reset operation cannot be carried out, it becomes impossible for the processor 22 to carry out the reset operations.
Thus, with the conventional reset circuit 101, the reset trigger signal CPURSTB and the output of the inverter circuit 9 are entered to the AND gate circuit 10, and the output of the AND gate circuit 10 is output as the reset output signal RSTB, such that the reset output signal RSTB is directly output by way of a ‘through outputting’.
By this configuration, the reset trigger signal CPURSTB may be directly sent as a ‘through output’ and output as the reset output signal RSTB. However, if the reset trigger signal CPURSTB is sent as ‘through output’ in this manner, the problem as now explained may be produced when the clock inputting is taking place normally.
In general, the PIO port acts as an input port during the resetting of e.g., a processor, and hence is in a high impedance state. Thus, a pull-up resistor or a pull-down resistor is connected in circuit for prescribing the level of negation of the reset trigger signal if, in case the PIO port is set as an output port and used for outputting the reset trigger signal, the processor is being reset. In the conventional technique, shown in FIG. 5, ‘H’ is the level of negation, and hence a pull-up resistor 29 is connected to the reset trigger signal CPURSTB.
If reset is entered to the processor 22 itself the instant the processor 22 has asserted the reset trigger signal CPURSTB, such that the processor 22 has discontinued to assert the reset trigger signal CPURSTB, the reset trigger signal CPURSTB undergoes transitions to the negated state over some time through the pull-up resistor 29.
However, with the reset extension circuit 3, shown in FIG. 7, the D-flip-flops 311, 312, counter circuit 32 and the JK flip-flop circuit 33 are provided for the input signal IN, so that, if the reset extension is to be carried out normally, it is necessary to adjust the constant of the pull-up resistor 29 in such a manner that the reset trigger signal CPURSTB will be in the ‘L’ state for at least two clocks or for a longer time as from the time the reset signal is entered to the processor 22.
FIG. 9 shows a timing chart in case reset extension has been carried out normally by adjusting the pull-up resistor 29. In FIG. 9, the reset trigger signal RSTB is kept in the ‘L’ state at timings T1, T2 when two clocks have as yet not elapsed as from a timing of T0 when the reset trigger signal RSTB has become ‘L’. Consequently, the reset output signal RSTB follows a scheduled operation of transition in which the signal takes on the level ‘L’ at the timing of T0 and subsequently takes on the level ‘H’ after lapse of the predetermined time.
However, if the constant of the pull-up resistor 29 or the value of the device capacitance is too low, it may be an occurrence that the time of two clocks is not guaranteed as the time duration in which the reset trigger signal CPURSTB remains in the ‘L’ state. FIGS. 10 and 11 depict the timing charts for such case.
FIG. 10 shows a case wherein the reset trigger signal CPURSTB transitions to ‘L’ and then reverts to ‘H’ before detection of the next rise edge of the clock signal, with the result that the reset extension circuit 3 is unable to detect the reset trigger signal CPURSTB such that it is unable to perform reset extension. FIG. 11 shows a case wherein the time of two clocks is not guaranteed as the time duration during which the reset trigger signal CPURSTB is ‘L’, with the result that the reset output is transiently negated.
In FIG. 10, the reset trigger signal CPURSTB at timing of T0 transitions to ‘L’ indicating the asserted state and reverts at timing of T1 to a level at which the signal is determined to be ‘H’. Thus, even though the AND gate circuit 10 detects that the reset trigger signal CPURSTB has transitioned to ‘L’, such that the reset output signal RSTB keeps on to be ‘L’ as from timing of T0 until timing of T1, the reset extension circuit 3 is unable to detect that the reset trigger signal CPURSTB has transitioned to ‘L’, such that no reset extension is carried out. The result is that the reset trigger signal CPURSTB is negated at the timing of T1 and hence the time during which the reset output signal RSTB keeps onto be in the ‘L’ state becomes shorter such that the reset time prescribed by the devices cannot be achieved.
FIG. 11 shows a case wherein the signal level of the reset trigger signal CPURSTB sufficient to verify the signal to be in the ‘L’ state can be maintained only until lapse of one clock as from the time the signal CPURSTB has transitioned to ‘L’. In FIG. 11, the reset trigger signal CPURSTB at timing of T0 takes on the level ‘L’ indicating the asserted state and maintains the ‘L’ level at timing of T1. However, the reset trigger signal is unable to maintain the ‘L’ level at timing of T3. Hence, the reset extension cannot be achieved normally and, at timing of T2 when the reset trigger signal CPURSTB has been determined to be ‘H’, the reset output signal RSTB transiently takes on the level ‘H’ indicating the negated state and again takes on the level ‘L’ at timing of T3.
In any of the above-described cases of FIGS. 10 and 11, it is not assured that the reset output signal RSTB takes on the level ‘H’, indicating the asserted state, for a prescribed time duration, with the result that malfunction is produced, depending on device types. It may be an occurrence that a package performs unpredictable operations. Thus, with the conventional reset circuit 101, the state of ‘L’ of the reset trigger signal CPURSTB is guaranteed, by adjusting the constant of the pull-up resistor or the pull-down resistor, until such time that two clocks have elapsed as from the transitioning of the reset trigger signal CPURSTB to ‘L’, lest the above-described problem should be produced.
When the clocks are stopped at the time the power supply is turned on, the conventional reset circuit 101 suffers from a problem different from the above-described problem. If clocks are present on power up, data values or input/output settings of input/output ports of e.g., processors do not become indefinite even if the clocks are subsequently stopped, such that the reset output signal RSTB is not fixed at ‘L’ even if the reset trigger signal CPURSTB is output as ‘through-signal’ for operating as the reset output signal RSTB. However, when the clocks are stopped on power up due e.g., to malfunctions, the PIO port and neighboring circuitry of the processor 22 cannot be reliably initialized and becomes destabilized. Consequently, the PIO port, which should inherently be set to high impedance during reset, is likely to take on an output mode to become fixed in the state of asserting the reset trigger signal CPURSTB to the reset circuit 101, that is, in the ‘L’ state. FIG. 12 shows a timing chart for such case.
In FIG. 12, the power supply is turned on as the clock stop detection signal CALMB is ‘L’, that is, with the clock signals in the stopped state, and the reset trigger signal CPURSTB is fixed at ‘L’. With the conventional reset circuit 101, shown in FIG. 6, the reset trigger signal CPURSTB is directly supplied in such state to the AND gate circuit 10, so that the reset output signal RSTB is also fixed at ‘L’, that is, in the asserted state. Consequently, the reset signal, supplied to the status monitor unit 20, keeps on to be asserted, and hence the status monitor unit is unable to report the stop of the clock signals to the upper order state monitor unit 27.
Heretofore, a large variety of circuit configurations have been proposed as a reset circuit for generating reset signals. For example, there has been proposed a reset circuit for preventing malfunctions by shifting the supply timing of the reset signal to various circuits architecting the system (for example, see JP Patent Kokai Publication JP-P2001-142792A). However, there lacks up to now a reset circuit capable of solving the above problems.
The above-described conventional reset circuit suffers the following problems:
(1) Except if it is determined that the asserted state persists for not less than two clocks in the least as from the time the reset signal is entered to the processor, a normal reset extension operation cannot be achieved. Hence, it becomes necessary to adjust the constant of the pull-up resistor coupled to the reset trigger signal.(2) If the power supply is turned on as the clock signals are stopped, such that the reset trigger signal keeps on to be asserted, the state monitor unit is also reset and hence is unable to report the stopped state of the clock signals to the upper order monitor unit.
It is an object of the present invention to provide a reset circuit in which, as the function of outputting the reset trigger signal in a ‘through’ fashion in case the clocks of the reset circuit are stopped, and the function of stopping the reset extension when the clocks are stopped during the reset extension, are left, the necessity for adjusting the constant of the pull-up resistor or the pull-down resistor of the reset trigger signal is eliminated to assure a reliable reset operation.
It is another object of the present invention to provide a reset circuit in which, even when clocks are stopped on power up such that the PIO port of e.g., a processor takes on the output mode, with the reset trigger signal becoming fixed in the asserted state, the reset may be canceled to enable the operation of the status monitor unit.